Ultra shallow junctions <500 Å with steep profiles <8 nm/decade are required for device technologies ⩽0.13 μm as outlined by the recent ITRS Roadmap. For a p+/n junction such profiles can be obtained using sub-keV B ion implantation since both the projected range and more importantly the transient enhanced diffusion are significantly reduced at lower energies. State-of-the-art high current implanters utilize a deceleration mode typically for sub 1 keV implantation in order to increase the beam current and production wafer throughput. Such a mode contains a very low level of energy contamination. This level is measured for sub keV B implants in the Quantum Leap and factors affecting the level of contamination are studied. Spike and soak annealing reduces the effect of the energy contamination on junction profile and depth. The effect of energy contamination on device performance such as Leff, VT and I DSAT is simulated using ISE TCAD
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